Semiconductor device manufacturing methods

ABSTRACT

Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.

TECHNICAL FIELD

The present invention relates generally to the fabrication ofsemiconductor devices, and more particularly to the fabrication oftransistors and other features.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as examples. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductive layers of material over asemiconductor substrate, and patterning the various layers usinglithography to form circuit components and elements thereon.

Optical photolithography involves projecting or transmitting lightthrough a pattern made of optically opaque areas and optically clearareas on a lithography mask or reticle. For many years in thesemiconductor industry, optical lithography techniques such as contactprinting, proximity printing, and projection printing have been used topattern material layers of integrated circuits. In optical lithography,lens projection systems and transmission lithography masks are used forpatterning, wherein light is passed through the lithography mask toimpinge upon a photosensitive material layer disposed on a semiconductorwafer or workpiece. The patterned photosensistive material layer is thenused as a mask to pattern a material layer of the workpiece.

A transistor is an element that is utilized extensively in semiconductordevices. There may be millions of transistors on a single integratedcircuit (IC), for example. A common type of transistor used insemiconductor device fabrication is a metal oxide semiconductor fieldeffect transistor (MOSFET). A transistor typically includes a gatedielectric disposed over a channel region, and a gate formed over thegate dielectric. A source region and a drain region are formed on eitherside of the channel region within a substrate or workpiece.

A complementary metal oxide semiconductor (CMOS) device is a device thatutilizes p channel metal oxide semiconductor (PMOS) field effecttransistors (FETs) and n channel metal oxide semiconductor (PMOS) fieldeffect transistors (FETs) in a complementary arrangement. One example ofa memory device that uses both PMOS FETs and NMOS FETs is a staticrandom access memory (SRAM) device. A typical SRAM device includesarrays of thousands of SRAM cells, with each SRAM cell having four orsix transistors, for example. A commonly used SRAM cell is asix-transistor (6T) SRAM cell, which has two PMOS FETs interconnectedwith four NMOS FETs.

One challenge in transistor manufacturing processes is the patterning ofthe transistor gates. Reducing the final tip-to-tip (T2T) distance ofgate conductor line ends in SRAM cells to the desired target values hasbecome one of the major patterning challenges for CMOS technologies withsmaller ground rules, for example. Limitations in optical resolution andspace angle dependent variations in etch/redeposition processes mayresult in device features not printing in desired shapes or sizes.Efforts to compensate for line end shortening in patterned devicestructures by length corrections of corresponding mask features may berestricted by geometrical limitations on the mask or limited resolutioncapability of the exposure tool.

Thus, what are needed in the art are improved methods of patterningtransistor gates and other features of semiconductor devices.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention, which provide novel methods of reducingtip-to-tip distance between features by optimizing lithography andreactive ion etch (RIE) processes.

In accordance with a preferred embodiment of the present invention, amethod of processing a semiconductor device includes providing aworkpiece having a material layer to be patterned disposed thereon. Amasking material is formed over the material layer of the workpiece. Themasking material includes a lower portion and an upper portion disposedover the lower portion. The upper portion of the masking material ispatterned with a first pattern. An additional substance is introducedand the lower portion of the masking material is patterned. The maskingmaterial and the additional substance are used to pattern the materiallayer of the workpiece.

The foregoing has outlined rather broadly the features and technicaladvantages of embodiments of the present invention in order that thedetailed description of the invention that follows may be betterunderstood. Additional features and advantages of embodiments of theinvention will be described hereinafter, which form the subject of theclaims of the invention. It should be appreciated by those skilled inthe art that the conception and specific embodiments disclosed may bereadily utilized as a basis for modifying or designing other structuresor processes for carrying out the same purposes of the presentinvention. It should also be realized by those skilled in the art thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a top view of a lithography mask in accordance with apreferred embodiment of the present invention, having a pattern for aplurality of transistor gates formed thereon;

FIGS. 2 through 6 show cross-sectional views of a method of patterning aplurality of gates using the lithography mask of FIG. 1 in accordancewith a preferred embodiment of the present invention;

FIG. 7 shows a top view of a semiconductor device that has beenpatterned using the lithography mask of FIG. 1 and the methodillustrated in FIGS. 2 through 6;

FIG. 8 shows a top view of a lithography mask in accordance with anotherpreferred embodiment of the present invention;

FIGS. 9 through 12 show cross-sectional views of a method of patterninga plurality of gates using the lithography mask of FIG. 8 in accordancewith a preferred embodiment of the present invention;

FIG. 13 shows a top view of a semiconductor device that has beenpatterned using the lithography mask of FIG. 8 and the methodillustrated in FIGS. 9 through 12;

FIGS. 14 and 15 show top views of lithography masks in accordance withyet another preferred embodiment of the present invention;

FIGS. 16 through 18 show perspective views of a method of patterning aplurality of gates using the lithography masks of FIGS. 14 and 15 inaccordance with a preferred embodiment of the present invention;

FIG. 19 shows a top view of the semiconductor device shown in FIG. 18;and

FIG. 20 shows a perspective view, and FIG. 21 shows a top view of asemiconductor device that has been patterned using the lithography masksof FIGS. 14 and 15 and the method illustrated in FIGS. 16 through 19.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that maybe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely in the patterning oftransistor gates of SRAM devices. The invention may also be applied,however, to the patterning of other features of semiconductor devices,particularly features having a repeating pattern, wherein positioningthe features closer together in a controlled manner is desired.Embodiments of the invention may also be implemented in othersemiconductor applications such as other types of memory devices, logicdevices, mixed signal devices, and other applications, as examples.

Reducing the tip-to-tip distance between transistor gates is a keychallenge for achieving high density, particularly in applications suchas SRAM devices. Both a small pitch (e.g., between elongated edges) andsmall tip-to-tip distance (e.g., between short edges) between adjacentgates are required in some designs. However, there are limitations inexisting lithography capabilities in printing small tip-to-tipdistances. In some etch processes, the etch process itself contributesto a line end shortening effect, for example.

Embodiments of the present invention provide methods for reducingetch-related line end shortening effects. The size of the features ismade slightly larger using several methods or combinations thereof, tobe described further herein, resulting in reducing the space between thefeatures. In some embodiments, the size of the features is slightlyenlarged by the selection of the gas chemistries used to open ananti-reflective coating (ARC) disposed beneath a layer of photosensitivematerial, resulting in a redeposition of etch-protective material on thesidewalls of the ARC, which slightly enlarges features formed in amaterial layer and reduces the space between features. In otherembodiments, the size of the features is slightly enlarged by theintroduction of a polymer material after the patterning of thephotoresist but before the opening of the anti-reflective coating. Thepolymer material coats the patterned photosensitive material sidewalls,making the patterns formed in the anti-reflective coating and thepatterned material layer slightly larger and also reducing the spacebetween the features.

A first preferred embodiment of the present invention will be describedwith reference to FIGS. 1 through 7, in which an etch chemistry used toopen an anti-reflective coating is selected that has a redepositioncomponent during the etch process. Referring first to FIG. 1, alithography mask 101 is shown in a top view. The lithography mask 101comprises a bright field binary mask that includes a substantiallyopaque material 105 attached or coupled to a substantially transparentmaterial 103. The substantially opaque material 105 preferably comprisesa material that is opaque to light or energy, such as chromium or otheropaque material. The substantially transparent material 103 preferablycomprises a transparent material such as quartz or glass, although othermaterials may also be used. The lithography mask 101 may also comprisean alternating phase shift mask, an attenuating mask, a dark field mask,or other types of masks, as examples, not shown.

The opaque material 105 of the lithography mask 101 in accordance with apreferred embodiment of the present invention comprises a pattern for aplurality of transistor gates formed thereon. The pattern preferablycomprises a plurality of opaque features formed in the opaque material105. The patterns for the features comprised of the opaque material 105are preferably arranged in a plurality of rows and columns, as shown inFIG. 1. The patterns for the features may comprise a plurality of opaquesubstantially rectangular shapes having rounded ends, or the featurepatterns may comprise other shapes, such as a plurality of square,round, elliptical, triangular, rectangular, polygonal, or trapezoidalfeatures. Alternatively, the patterns for the features in the opaquematerial 105 may also comprise other shapes, for example. The rows andcolumns of the feature patterns may be staggered, e.g., in alternatingrows or columns in pairs, as shown, staggered singularly (not shown), oralternatively, the feature patterns may be aligned singularly or inpairs (see FIG. 8) in rows and columns. The pattern features may also bearranged in other configurations, for example.

In some embodiments, the patterns for the features preferably comprise awidth (e.g., dimension d₁) along at least one side comprising a minimumfeature size of the lithography system the manufacturing process will beused in, and the patterns for the features may be spaced apart by thesame minimum feature size, as an example. The width d₁ and spaces mayalso comprise dimensions greater than the minimum feature size,alternatively. The patterns for the features in the opaque material 105comprise a length represented by dimension d₂. The length-wise ends ofthe patterns for the features in the opaque material 105 are separatedfrom adjacent patterns for features by a tip-to-tip dimensionrepresented by dimension d₃. The patterns for the corresponding featureson the semiconductor device, after being multiplied by thedemagnification (reduction) factor of the exposure tool, which isgenerally 4, as an example (although exposure tools with other reductionfactors or 1:1 ratios may also be used), may comprise a width ordimension d₁ of about 100 nm or less, a length or dimension d₂ of about500 nm or less, and a tip-to-tip distance or dimension d₃ of about 150nm or less in some applications, as examples, although the patterns forthe features in the opaque material 105 of the mask 101 may alsocomprise other dimensions.

Note that the patterns for features in the opaque material 105 of thelithography mask 101 may also include small protrusions or serifs alongtheir length or at their ends, for optical proximity correction (OPC) inthe lithography process, for example, not shown. The OPC structures arenot printed on a material layer during a lithography process, butrather, accommodate at least partially for diffraction effects in thelithography process and system.

FIGS. 2 through 6 show cross-sectional views of a method of patterning aplurality of transistor gates using the lithography mask 101 of FIG. 1in accordance with a preferred embodiment of the present invention,wherein an anti-reflective coating open etch step is optimized tocontrol the amount of line end shortening. FIG. 2 illustrates across-sectional view of a semiconductor device 100 patterned using thelithography mask 101 at “2-2” in FIG. 1, for example.

To manufacture a semiconductor device 100 using the lithography mask 101of FIG. 1, first, a workpiece 102 is provided. The workpiece 102 mayinclude a semiconductor substrate comprising silicon or othersemiconductor materials covered by an insulating layer, for example. Theworkpiece 102 may also include other active components or circuits, notshown. The workpiece 102 may comprise silicon oxide over single-crystalsilicon, for example. The workpiece 102 may include other conductivelayers or other semiconductor elements, e.g., transistors, diodes, etc.Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may beused in place of silicon. The workpiece 102 may comprise asilicon-on-insulator (SOI) substrate, for example.

A material layer 104/106 to be patterned is formed over the workpiece102. The material layer 104/106 may comprise a gate dielectric material104 disposed over the workpiece 102 and a gate material 106 disposedover the gate dielectric material 104, as examples, althoughalternatively, the material layer 104/106 may comprise other materials.The gate dielectric material 104 may comprise an insulating materialsuch as silicon dioxide, silicon nitride, a high dielectric constant (k)material, or combinations or multiple layers thereof, as examples. Thegate dielectric material 104 may comprise a thickness of about 300Angstroms or less, for example. The gate material 106 may comprise asemiconductive material such as polysilicon or a conductor such as ametal, or combinations or multiple layers thereof, as examples. The gatematerial 106 may comprise a thickness of about 2,000 Angstroms or less,for example. Alternatively, the gate dielectric material 104 and thegate material 106 may comprise other materials and dimensions. Thematerial layer 104/106 may also include an optional hard mask disposedover the gate material 106, for example, not shown. The material layer104/106 may comprise a nitride material layer disposed proximate a topsurface thereof that is used as a mask for a later etch process, asanother example, also not shown.

A masking material 110/114 is formed over the material layer 104/106 tobe patterned, as shown in FIG. 2. The masking material 110/114preferably comprises an anti-reflective coating 110 disposed over thematerial layer 104/106, and a layer of photosensitive material 114disposed over the anti-reflective coating 110. The anti-reflectivecoating 110 is also referred to herein as a-lower portion 110 of themasking material 110/114. The anti-reflective coating 110 may comprisean organic material, for example, although other materials may also beused. The masking material 110/114 may include an optional organicdielectric layer (ODL) also comprising an organic material disposedbeneath the anti-reflective coating 110 in embodiments, not shown. Thelayer of photoresist 114 is also referred to herein as an upper portion114 of the masking material 110/114, for example.

The upper portion 114 of the masking material 110/114 is patterned witha first pattern, as shown at 114 a, using the lithography mask 101 shownin FIG. 1. The first pattern comprises substantially the same shape asthe pattern in the opaque material 105 of the lithography mask (e.g.,before OPC structures are added to the mask 101), for example. The firstpattern may exhibit line shortening of pattern features of thelithography mask 101 in some embodiments, for example. The maskingmaterial 110/114 is exposed to light or energy through or reflected fromthe mask 101 to expose portions of the layer of photoresist 114 notprotected by the mask 101, leaving portions 114 a of the layer ofphotoresist 114 unexposed. The layer of photoresist 114 is thendeveloped, and exposed portions of the layer of photoresist 114 areetched away, as shown in FIG. 3.

Next, an additional substance is introduced and the lower portion 110,e.g., the anti-reflective coating 110 of the masking material 110/114 ispatterned or opened using an etch process 116, as shown in FIG. 3. Inthis embodiment, the additional substance 117 that is introducedcomprises a by-product of the etch process 116 used to pattern the lowerportion of the masking material 110. The etch process 116 preferablycomprises a reactive ion etch (RIE) process that preferably comprises aredeposition component 117 (e.g., also referred to herein as anadditional substance 117) that redeposits, lines, or forms on sidewallsof the anti-reflective coating 110 as the anti-reflective coating 110 isetched away, for example. The semiconductor device 100 is shown in FIG.4 after the etch process 116 for the anti-reflective coating 110 iscompleted.

The redeposition component 117 may comprise a dimension d₄ of about 20nm or less of a material such as a polymer material. The redepositioncomponent 117 preferably comprises a polymer, and may comprise C—F—O—Si,or a material comprising C, F, O, Si, or combinations thereof, asexamples. Alternatively, the redeposition component 117 may alsocomprise other dimensions and materials. The redeposition component 117preferably comprises a material that is resistant to the etchchemistries that are used later to pattern the material layer 104/106,for example.

The etch process 116 is preferably selected to achieve a desiredmaterial type and thickness of the redeposition component 117, inaccordance with embodiments of the present invention. For example, in apreferred embodiment, a pure carbon fluorine oxygen (CF₄/O₂) gaschemistry is used as the gas chemistry for the etch process 116. Inanother preferred embodiment, CF₄/CH₂F₂/O₂ may be used for the etchprocess 116, as another example. Alternatively, other gas chemistriesmay be used for the etch process 116, such as othercarbon-fluorine-oxygen gas chemistries or other gas chemistries.

The material layer 104/106 is then patterned using the layer ofphotoresist 114, the additional substance 117, the optional ODL ifpresent, and the anti-reflective coating 110 as a mask, while exposedportions of the material layer 104/106 are etched away. A portion of orthe entire layer of photoresist 114 may be consumed or removed duringthe etch process to pattern the material layer 104/106, as shown in FIG.5. Any remaining anti-reflective coating 110 and photoresist 114 arethen removed.

The pattern formed in the material layer 104/106 comprises a secondpattern, wherein the second pattern is larger than the first pattern ofthe layer of photoresist 114. The second pattern may comprise a slightenlargement of the first pattern, for example. The enlarged secondpattern may provide a slight enlargement of the first pattern toaccommodate for line shortening during the transfer of the mask 101pattern to the layer of photoresist 114, for example. Or, the secondpattern may intentionally be slightly larger than the first pattern inorder to reduce the tip-to-tip distance d₈ between adjacent features inthe material layer 104/106, as another example, as shown in FIG. 6.

Because of the increased width, shown as dimension d₅ in FIGS. 4 and 5,of the anti-reflective coating 110 by the width or dimension d₄ of theadditional substance or redeposition component 117, the width of thefeatures formed in the material layer 104/106 also comprises a width ordimension d₅, as shown in FIG. 5. The widths (dimension d₅) of thefeatures formed in the material layer 104/106 are shown, which areslightly larger that the widths (dimension d₁) of the feature patternsof the lithography mask 101 in FIG. 1, e.g., by an amount d₄ on eitherside.

Note that the material layer 104/106 may comprise a single layer ofmaterial rather than two material layers 104 and 106, as shown.Furthermore, only the gate material 106 may be patterned using themethods described herein, leaving the gate dielectric material 104unpatterned (not shown). The gate dielectric material 104 may bepatterned in a later manufacturing step in these embodiments, forexample.

In FIG. 6, a cross-sectional view of the semiconductor device 100 ofFIG. 5 is shown rotated by ninety degrees. FIG. 7 shows a top view of asemiconductor device 100 that has been patterned using the lithographymask 101 of FIG. 1 and the method illustrated in FIGS. 2 through 6. Thelengths (dimension d₇) of the features formed in the material layer104/106 are shown in FIGS. 6 and 7. The lengths (dimension d₇) of thefeatures are slightly larger than the lengths (dimension d₂) of thefeature patterns on the mask 101, e.g., by an amount d₆ on either side.Note that isolation regions 118, which may comprise shallow trenchisolation (STI) or other type of isolation structures, are also shown inFIG. 6 and in FIG. 7 in phantom. The amount of overlap of transistorgates (e.g., features formed in the gate material 106) with isolationregions 118 and/or active areas can be a critical dimension in asemiconductor device 100 design, for example, and embodiments of thepresent invention provide increased control of such overlaps withunderlying structures, and a reduction of the line shortening effect onpatterned features.

Advantageously, the features formed in the material layer 104/106 arespaced apart by a decreased amount or tip-to-tip dimension d₈, as shownin FIG. 6. Because the ends of the features have been lengthened byamount d₆ (see FIG. 5) due to the novel redeposition component oradditional substance 117 of the etch process 116, the tip-to-tipdimension d₈ is decreased compared with the tip-to-tip dimension d₃ ofthe pattern on the mask 101, forming a more dense array of transistorgates 106, for example.

Experimental results show that due to the shape of the feature patternsof the lithography mask 101 and due to the nature of the etch processused to pattern the material layer 104/106, narrower portions of thefeatures (the width, d₅) may tend to not be increased in size as much aslonger portions (the length, d₇) of the features are increased. Forexample, dimension d₆ of the amount of increase of the length d₇ of thefeatures may be greater than dimension d₄ of the amount of increase ofthe width d₅, advantageously, in accordance with this embodiment of thepresent invention.

Table 1 shows experimental results after the novel optimization of theanti-reflective coating 110 open etch step of the first embodiment ofthe present invention for two SRAM cells, SRAM cell A and SRAM cell B,using two etch processes. The manufacturing method provides a highamount of leverage for minimizing etch-induced line end shortening. Forexample, Table 1 shows the variation of line width for polysilicon gatesand tip-to-tip distance as a function of the ARC 110 open gas chemistry(e.g., for the etch process 116).

TABLE 1 Final CD Final CD Develop CD of Process A of Process B SRAM cellA SRAM NFET 107.5 92.1 75.9 SRAM PFET 106.4 95.1 80.1 Tip-to-tip 105.9174.7 140.6 Line end pull 4.5 1.1 Back ratio (LEPBR) SRAM cell B SRAMNFET 114.7 96.2 78.4 SRAM PFET 107.1 97.1 82.3 Tip-to-tip 89.5 161.5130.2 LEPBR 3.9 1.1

Table 1 shows the line end pull-back ratio (LEPBR), i.e., the ratio ofthe final line end pull-back vs. the lateral critical dimension (CD)reduction/edge for two different gases chemistries used for the ARC openetch process 116, wherein process A comprised CHF₃/HBr/He/O₂ and processB comprised CF₄/CH₂F₂/O₂. In one experiment, a tip-to-tip distancedifference resulting from the two processes resulted in a largedifference of about 60 nm.

Line ends of features are more easily accessible to etching and also forpolymer deposition, due to the comparatively larger space angle fromwhich impinging species can arrive from the gas phase. By properlybalancing the competing processes of etch attack and polymer material(e.g., of the redeposition component 117) deposition, LEPBR values ofclose to 1 can be obtained, as shown for process B. Note that the use ofhighly polymerizing etch processes may reduce the average trim amount(e.g., the litho-etch CD offset) and therefore may require an adjustmentof the lithography CD target towards lower values, requiring improvedresolution capability.

Moreover, the variation of the etch bias as a function of pitch may beeffected. Etch bias data results from experiments indicated a similarthrough-pitch behavior for etch processes with a varying degree ofpolymer deposition. A gradual decrease in etch bias is observable withincreasing pitch from the smallest pitch towards a pitch range around400-500 nm, for example.

A reduction in tip-to-tip distance (e.g., dimension d₈ in FIGS. 6 and 7)of about 20 to 30 nm was achieved in experimental results by the properselection of the ARC material 110 open etch process 116, advantageously.Also advantageously, experimental results show that the tip-to-tipdimension may be reduced faster than the line width increases using thefirst embodiment described herein, for example.

Thus, in accordance with the first embodiment of the present invention,patterns are made slightly larger by selecting an etch process 116 foropening the ARC material 110 that has a redeposition component 117 thatslightly increases the size of the features patterned. In accordancewith a second and third embodiment of the present invention, patternsare made slightly larger by an additional deposition process to form athin material 220 (see FIG. 10) and 320 (see FIG. 18) over and lining apatterned portion of the masking material, to be described furtherherein.

A second embodiment of the present invention will be described next withreference to FIGS. 8 through 13. Like numerals are used for the variouselements that were used to describe FIGS. 1 through 7. To avoidrepetition, each reference number shown in FIGS. 8 through 13 is notdescribed again in detail herein. Rather, similar materials x02, x04,x06, x08, etc. . . . are preferably used for the various material layersshown as were used to describe FIGS. 1 through 7, where x=1 in FIGS. 1through 7 and x=2 in FIGS. 8 through 13.

A lithography mask 201 is shown in FIG. 8 comprising a pattern formed inan opaque material 205 of the mask 201 comprising rows and columns ofpairs of gate patterns. The feature patterns comprise a width ofdimension d₁, and length of dimension d₂, and a tip-to-tip distancebetween adjacent ends of dimension d₃.

The lithography mask 201 is used to pattern an upper portion 214 of amasking material 210/214 formed over a material layer 204/206 of asemiconductor device 200, as shown in FIG. 9. An additional substance220 is introduced, and the lower portion 210 of the masking material210/214 is patterned. In this embodiment, the additional substance 220preferably comprises a polymer material that is formed over thepatterned upper portion of the masking material and over the lowerportion of the masking material, before patterning the lower portion ofthe masking material 210, as shown in FIG. 10. The polymer material 220is preferably conformally deposited, equally covering all exposedportions of the anti-reflective coating 210 and the patternedphotosensitive material 214, as shown.

The polymer material 220 preferably comprises a material that isresistant to the etch process used to open or pattern theanti-reflective coating material 210, for example. The etch process forthe anti-reflective coating 210 is preferably anisotropic, resulting ina portion of the polymer material 220 remaining on the sidewalls of thephotosensitive material 214, as shown in FIG. 11. The polymer material220 preferably comprises a thickness d₉ of about 20 nm or less in someembodiments, although alternatively, the polymer material 220 maycomprise other dimensions. The polymer material 220 preferably comprisesC—F—O—Si, or a material comprising C, F, O, Si, or combinations thereof,as examples, although other materials may also be used.

The polymer material 220 may be formed by introducing a gas such asC₄F₈, C_(x)H_(y)F_(z), other C—F based gases, or other gases, to theetch chamber the semiconductor device 200 is being processed in, whileapplying a small bias power, e.g., about 20 to 50 Watts, although otherlevels of bias power may also be used, and turning on a plasma source,resulting in the formation of the polymer material 220, as an example.Alternatively, the polymer material 220 may be formed using depositionor growth methods, as examples.

The masking material 210/214 and the polymer material 220 on thesidewalls of the photosensitive material 214 are used as a mask whileportions of the material layer 204/206 are etched away, as shown in FIG.12. The masking material 210/214 and the polymer material 220 are thenremoved. The etch process of the material layer 204/206 preferablycomprises an anisotropic, directional etch process that results in aportion of the polymer material 220 being left remaining on thesidewalls of the photosensitive material 214 during the patterning ofthe underlying material layer 204/206, enlarging the pattern of thematerial layer 204/206-by the thickness of the polymer material 220 onall sides. The pattern of the material layer 204/206 comprises a widthor dimension d₁₀ in the cross-sectional view shown in FIG. 12, whereinthe dimension d₁₀ is greater than the width of the upper portion 214 ofthe masking material by about twice the amount of the thickness d₉ ofthe polymer material 220, for example.

FIG. 13 shows a top view of a semiconductor device 200 patterned usingthe method shown in FIGS. 8 through 12, illustrating the patterned gatematerial 206. The patterned gate material 206 has an extended or greaterlength (dimension d₁₁) compared to the feature pattern length (dimensiond₂) of the mask 201 shown in FIG. 8, e.g., divided by a reduction factorif other than a 1:1 mask and exposure tool is used. The patterned gatematerial 206 has a reduced or shortened tip-to-tip distance (dimensiond₁₂) compared to the feature pattern tip-to-tip distance (dimension d₃)of the mask 201, divided by the reduction factor. The patterned gatematerial 206 also has an extended or greater width (dimension d₁₃)compared to the feature pattern width (dimension d₁) of the mask 201,due to the presence of the polymer material 220 on the sidewalls of thephotosensitive material 214 during the etch process.

Thus, the second embodiment of the present invention provides anothermethod of decreasing line end shortening and decreasing the tip-to-tipdistance between features formed in a material layer 206. Furthermore,the second embodiment may also be combined with the first embodiment;for example, the polymer material 220 may be deposited over thepatterned layer of photoresist 214, and an etch process such as the etchprocess 116 described for the first embodiment may be used that alsoforms a redeposition component 117 on the sidewalls of theanti-reflective coating 210 during the etching of the anti-reflectivecoating 210, further enlarging the features formed in the material layer204/206.

Note that an optional ODL may be included in the masking material210/214 in the second embodiment, e.g., disposed beneath theanti-reflective coating 210, not shown, e.g., if the masking material210/214 comprises a tri-layer photoresist.

A third embodiment of the present invention will be described next withreference to FIGS. 14 through 21. Again, like numerals are used for thevarious elements that were described in FIGS. 1 through 7 and 8 through13, and to avoid repetition, each reference number shown in FIGS. 14through 21 is not described again in detail herein.

In this embodiment, a two step etch process is used to pattern thematerial layer 306, using two lithography masks and two masking materiallayers. FIGS. 14 and 15 show top views of lithography masks 301 a and301 b in accordance with the third embodiment of the present invention.A first lithography mask 301 a is shown in FIG. 14, and a secondlithography mask 301 b is shown in FIG. 15. The first lithography mask301 a may comprise a pattern 305 a for lengthwise portions of gateelectrodes, for example, defining the width (dimension d₁₄) of the gatesbut not the lengths. The second lithography mask 301 b may comprise a“cutter mask” that is adapted to define the length (dimension d₁₅) ofthe gates, e.g., the ends of the gates in a lengthwise direction.

The patterns in the lithography masks 301 a and 301 b preferablycomprise positive patterns in some embodiments, for example, wherein thepatterns in the opaque material 305 a and 305 b represent regions wherethe gate material 306 will remain residing after the two-step etchprocess, at the intersections of the patterns in the opaque material 305a and 305 b after the two-step etch process. Alternatively, the patternsmay comprise negative patterns (not shown).

Again, the widths of the patterns 305 a of the transistor widthdefinition mask 301 a comprise a dimension d₁₄. The widths of thepatterns in the opaque material 305 b of the cutter mask 301 b thatdefine the ends of the transistor gates, e.g., the length of the gates,comprise a dimension d₁₅. The tip-to-tip spacings on the mask 305 bbetween line ends of the gate lengths comprise a dimension d₁₆.

FIGS. 16 through 18 show perspective views of a method of patterning aplurality of gates using the lithography masks 301 a and 301 b of FIGS.14 and 15 in accordance with a preferred embodiment of the presentinvention. FIG. 16 shows a first masking material 310 a/314 a comprisingan anti-reflective coating 310 a disposed over a gate material 306 and aphotosensitive material 314 a disposed over the anti-reflective coating310 a, after the first lithography mask 301 a of FIG. 14 has been usedto pattern the first masking material 310 a/314 a, and after the firstmasking material 310 a/314 a has been used to pattern the gate material306 and the gate dielectric material 304, defining the widths of thegates 306. Note that the smaller sides of the gates 306 are oftenreferred to in the art as a “gate length.” However, for purposes of thisdiscussion, the smaller sides of the gates 306 are referred to herein aswidths. The widths of the gate material 306 and the gate dielectricmaterial 304 comprise substantially the same dimension d₁₄ (alsodimension d₁₉ in FIG. 21) as the widths of the patterns on the firstlithography mask 301 a, e.g., divided by the reduction factor.

Next, the first masking material 310 a/314 a is removed, and then asecond masking material 310 b/314 b is formed over the width-patternedgate material 306 and gate dielectric material 304, as shown in FIG. 17in a perspective view. The upper portion of the second masking material314 b is patterned using the second lithography mask 301 b shown in FIG.15, as shown.

A polymer material 320 preferably comprising similar materials andthickness as polymer material 220 shown in FIGS. 10 through 12 isdeposited or formed over the exposed portions of the workpiece 302. Thepolymer material 320 is formed over the patterned second maskingmaterial 314 b and over exposed portions of the second anti-reflectivecoating 310 b comprising the lower portion of the second maskingmaterial 310 b/314 b, similar to the second embodiment previouslydescribed herein, as shown in FIG. 18 in a perspective view and in FIG.19 in a top view. The polymer material 320 coats the patternedphotosensitive material 314 b, and preferably an etch process is used toopen the anti-reflective coating 310 b that is anisotropic and leavesthe polymer material 320 on the sidewalls of the patternedphotosensitive material 314 b.

The polymer material 320 enlarges the patterns of the second maskingmaterial 310 b/314 b to lengths comprising a dimension d₁₇, e.g., whichlengths d₁₇ are longer compared to the patterns 305 b on the secondlithography mask 301 b defining the lengths of the gate comprisingdimension d₁₅ shown in FIG. 15. The second masking material 310 b/314 band the polymer material 320 are used as a mask while the gate material306 and gate dielectric material 304 are patterned, leaving thestructure shown in a perspective view in FIG. 20 and shown in a top viewin FIG. 21. The tip-to-tip distance d₁₈ of the gates 306 has beenreduced, compared to dimension d₁₆ on the second lithography mask 301 b(see FIG. 15), e.g., by an amount substantially equal to twice thethickness of the polymer material 320.

Thus, using a two-step etch process, two lithography masks 301 a and 301b, and two masking materials 310 a/314 a and 310 b/314 b, the verticaland horizontal ends of the material layer 304/306 to be patterned may bedefined and patterned, wherein the length-wise distance between gates,the tip-to-tip distance, and line end shortening is reduced by theadditional deposition step of the polymer material 320, before the stepof opening the anti-reflective coating 310 b of the masking material 310b/314 b used for the patterning of the second lithography mask 310 b.Advantageously, because the “cutter mask” 301 b comprises a pattern thatis substantially rectangular, the ends of the transistor gates 306 maycomprise flat or squared edges 322, which may be advantageous in someapplications, for example.

In accordance with the third embodiment of the present invention, amethod of manufacturing a semiconductor device 300 preferably comprisesproviding a workpiece 302 as shown in FIG. 16, and forming a materiallayer such as gate material 306 (and optionally also gate dielectricmaterial 304) over the workpiece 302. A first anti-reflective coating310 a is formed over the workpiece 302, and a first photosensitivematerial 314 a is formed over the first anti-reflective coating 310 a.An optional first ODL may be disposed over the gate material 306 beforethe first anti-reflective coating 310 a is formed, if a tri-layer resistis used, for example, not shown.

The first photosensitive material 314 a and the first anti-reflectivecoating 310 a are exposed using the first lithography mask 301 a,wherein the first lithography mask 301 a comprises a first portion 305 aof a pattern. The first photosensitive material 314 a is developed,forming the first portion 305 a of the pattern in the firstphotosensistive material 314 a. The method includes using the firstphotosensitive material 314 a and/or the first anti-reflective coating310 a as a mask to form the first portion 305 a of the pattern in thematerial layer 306, as shown in FIG. 16.

The first photosensitive material 314 a and the first anti-reflectivecoating 310 a are removed, and a second anti-reflective coating 310 b isformed over the patterned material layer 306 and exposed portions of theworkpiece 302, as shown in FIG. 17. A second photosensitive material 314b is disposed over the second anti-reflective coating 310 b. An optionalsecond ODL may be formed before the second anti-reflective coating 310 bis formed, if a tri-layer resist is used, for example, not shown.

The second photosensitive material 314 b is exposed using a secondlithography mask 301 b, the second lithography mask 301 b comprising asecond portion 305 b of a pattern, the second portion of the pattern 305b comprising a different pattern than the first portion 305 a of thepattern of the first lithography mask and intersecting in regions withthe first portion 305 a of the pattern. The second photosensitivematerial 314 b is developed, forming the second portion 305 b of thepattern in the second photosensistive material 314 b, also shown in FIG.17.

The polymer material 320 is formed over the patterned secondphotosensitive material 314 b and over exposed portions of the secondanti-reflective coating 310 b, as shown in FIG. 18. Portions of thesecond anti-reflective coating 310 b are etched using the polymermaterial 320 and the patterned second photosensitive material 314 b as amask, using a directional, anisotropic etch process. The polymermaterial 320 and the patterned second photosensitive material 314 band/or the patterned second anti-reflective coating 310 b are then usedas a mask to pattern the material layer 306 of the workpiece 302 with anenlarged second portion 305 b of the pattern.

The first embodiment previously described herein may also be used incombination with the third embodiment. For example, the anisotropic etchprocess used to etch the second anti-reflective coating 310 b using thepolymer material 320 and the second photosensitive material 314 b mayinclude a redeposition component (such as 117 described for FIGS. 1through 7) that forms on sidewalls of the second anti-reflective coating310 b during the etch process. Patterning the material layer 306 in thisembodiment may further comprise using the redeposition component 117 asa mask during the patterning. The redeposition component 117 furtherenlarges the second portion 305 b of the pattern transferred to thematerial layer from the second lithography mask 301 b in thisembodiment, advantageously further reducing line end shortening anddecreasing the tip-to-tip distance between transistor gate ends.

Furthermore, in the third embodiment, a tapered profile may beintentionally introduced during the etch process to pattern the secondportion 305 b of the pattern, to further reduce the tip-to-tip distanced₁₈ without having an impact on the gate line (e.g., width or dimensiond₁₉ shown in FIG. 21) profile, advantageously, because the widths of thegates 306 are masked during the etching of the gate lengths. The taperedprofile may be introduced during the final etch process of the gatematerial 306, for example. The line ends of the gates 306 may benarrower at the top than at the bottom proximate the workpiece 302 inthese embodiments, so that the gate length at the bottom of the gates306 is increased and the tip-to-tip distance is decreased, for example,not shown.

Note that in the third embodiment, the order of the masks 301 a and 301b may be reversed: the second lithography mask 301 b may be used topattern the semiconductor device 300 first with the line end-definingpatterns 305 b and using the polymer material 320 to enlarge thepatterns 305 b, and then the first lithography mask 310 a may be used topattern the semiconductor device 300 with the gate width-definingpatterns 305 a.

Embodiments of the present invention have been described herein forapplications that utilize a positive photoresist, wherein the patternstransferred to the photoresist and also the material layer comprise thesame patterns on the lithography mask. Embodiments of the presentinvention may also be implemented in applications where a negativephotoresist is used, e.g., wherein the patterns transferred to thephotoresist and the material layer comprise the reverse image of thepatterns on the lithography mask.

The novel lithography methods and semiconductor device 100, 200, and 300manufacturing methods described herein may be used to fabricate manytypes of semiconductor devices 100, 200, and 300, including memorydevices and logic devices, as examples, although other types ofsemiconductor devices 100, 200, and 300, integrated circuits, andcircuitry may be fabricated using the novel embodiments of the presentinvention described herein. Embodiments of the present invention may beimplemented in lithography systems using light at wavelengths of 248 nmor 193 nm, for example, although alternatively, other wavelengths oflight may also be used.

The lithography masks 101, 201, 301 a, and 301 b described herein maycomprise binary masks, phase-shifting masks, attenuating masks, darkfield, bright field, transmissive, reflective, or other types of masks,as examples.

Advantages of embodiments of the invention include providing severalmethods for reducing line end shortening and reducing the tip-to-tipdistance (e.g., the space between ends of elongated features). Featuresthat are denser than the patterns on lithography masks mayadvantageously be manufactured using the novel methods described herein.Some embodiments involve the use of an etch process with a redepositioncomponent 117, requiring few manufacturing and process changes toimplement. Other embodiments require an additional deposition step(e.g., of polymer materials 220 and 320) and the use of an anisotropicetch process to ensure that a portion of the polymer materials 220 and320 remain on sidewalls of the photosensitive materials 214 and 314 bduring the anti-reflective coating 210 and 310 b open step.

Excellent control and reduction of the tip-to-tip distance may beachieved by the use of the novel embodiments of the invention describedherein. Many combinations of the embodiments described herein may beimplemented to achieve a desired line end shortening reduction orelimination, or a reduced tip-to-tip distance, for example. Tip-to-tipdistances that are smaller than the resolution limits of the opticallithography equipment and systems used to pattern the material layers106, 206, and 306 may be achieved by the novel methods described herein.

An unexpected result or advantage of the second and third embodimentsdescribed herein that utilize an intentionally deposited polymermaterial 220 and 320 introduced before the anti-reflective coating 210and 310 b open step is a reduction in the line end roughness (LER), dueto the presence of the polymer material 220 and 320 during the etchprocess to pattern the gate material 206 and 306, for example. A 10 to20% decrease in LER near the tops of gates 206 and 306 and a 5 to 8%decrease in LER near the bottoms of gates 206 and 306 (e.g., proximatethe workpiece 202 or 302) after the etch process used to pattern thegates 206 and 306 was observed in experimental test results, forexample.

Although embodiments of the present invention and their advantages havebeen described in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.For example, it will be readily understood by those skilled in the artthat many of the features, functions, processes, and materials describedherein may be varied while remaining within the scope of the presentinvention. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure of the present invention,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed, thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present invention. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

1. A method of processing a semiconductor device, the method comprising:providing a workpiece, the workpiece comprising a material layer to bepatterned disposed thereon; forming a masking material over the materiallayer of the workpiece, the masking material comprising a lower portionand an upper portion disposed over the lower portion; patterning theupper portion of the masking material with a first pattern; introducingan additional substance and patterning the lower portion of the maskingmaterial; and using the masking material and the additional substance topattern the material layer of the workpiece.
 2. The method according toclaim 1, wherein using the masking material and the additional substanceto pattern the material layer of the workpiece comprises forming asecond pattern in the material layer, the second pattern comprising anenlargement of the first pattern in the upper portion of the maskingmaterial.
 3. The method according to claim 1, wherein introducing theadditional substance and patterning the lower portion of the maskingmaterial comprises patterning the lower portion of the masking materialwith the first pattern and forming the additional substance on sidewallsof the lower portion of the masking material.
 4. The method according toclaim 1, wherein introducing the additional substance comprises liningthe lower portion of the masking material with a redeposition componentof a patterning process used to pattern the lower portion of the maskingmaterial.
 5. The method according to claim 1, wherein introducing theadditional substance comprises forming a polymer material over thepatterned upper portion of the masking material and over a top surfaceof the lower portion of the masking material, before patterning thelower portion of the masking material.
 6. The method according to claim1, wherein forming the masking material over the material layer of theworkpiece comprises forming a lower portion comprising ananti-reflective coating and forming an upper portion comprising aphotosensitive material.
 7. A method of manufacturing a semiconductordevice, the method comprising: providing a workpiece; forming a materiallayer to be patterned over the workpiece; disposing an anti-reflectivecoating over the material layer; disposing a layer of photosensitivematerial over the anti-reflective coating; patterning the layer ofphotosensitive material with a first pattern; introducing an additionalsubstance and patterning the anti-reflective coating; and using thelayer of photosensitive material, the additional substance, and theanti-reflective coating to pattern the material layer with a secondpattern, wherein the second pattern is larger than the first pattern. 8.The method according to claim 7, wherein introducing the additionalsubstance comprises introducing a by-product during the patterning ofthe anti-reflective coating, or wherein introducing the additionalsubstance comprises depositing a polymer material over the patternedlayer of photosensitive material, after patterning the layer ofphotosensitive material with the first pattern.
 9. The method accordingto claim 7, wherein the first pattern comprises a plurality of firstfeatures, the plurality of first features comprising a first distancefrom an end of one first feature to an end of an adjacent first feature,and wherein the second pattern comprises a plurality of second features,the plurality of second features comprising a second distance from anend of one second feature to an end of an adjacent second feature, thesecond distance being less than the first distance.
 10. The methodaccording to claim 9, wherein the plurality of second features comprisesa plurality of transistor gates.
 11. A semiconductor device manufacturedin accordance with the method of claim
 7. 12. The method according toclaim 7, wherein patterning the layer of photosensitive material withthe first pattern comprises using a single lithography mask or using aplurality of lithography masks.
 13. The method according to claim 7,further comprising disposing an organic dielectric layer (ODL) over thematerial layer before disposing the anti-reflective coating over thematerial layer, wherein patterning the anti-reflective coating furthercomprises patterning the ODL, and wherein patterning the material layerwith the second pattern further comprises using the ODL.
 14. A method ofpatterning a material layer of a semiconductor device, the methodcomprising: providing a workpiece, the workpiece comprising a materiallayer to be patterned disposed thereon; forming an anti-reflectivecoating over the material layer; forming a layer of photosensitivematerial over the anti-reflective coating; exposing the layer ofphotosensitive material using a lithography mask; developing the layerof photosensitive material; etching away portions of the layer ofphotosensitive material to form a first pattern in the layer ofphotosensitive material; etching the anti-reflective coating using thelayer of photosensitive material as a mask using an etch process,wherein the etch process includes a redeposition component that forms onsidewalls of the anti-reflective coating during the etch process,forming a second pattern in the anti-reflective coating and redepositioncomponent, the second pattern being larger than the first pattern; andpatterning the material layer of the workpiece with the second patternusing the layer of photosensitive material, the redeposition component,and the anti-reflective coating as a mask.
 15. The method according toclaim 14, wherein the etch process comprises a carbon fluorine-oxygengas chemistry, CF₄/O₂, or CF₄/CH₂F₂/O₂.
 16. The method according toclaim 14, wherein the redeposition component reduces line shortening offeatures formed in the material layer of the workpiece.
 17. The methodaccording to claim 14, wherein the first pattern comprises a pluralityof first features comprising a first width and a first length, whereinthe second pattern comprises a plurality of second features comprising asecond width and a second length, wherein the second length is greaterthan the first length, and wherein the second width is greater than thefirst width.
 18. The method according to claim 17, wherein the secondlength is greater than the first length by a first amount, and whereinthe second width is greater than the first width by a second amount, thefirst amount being greater than the second amount.
 19. A method ofpatterning a material layer of a semiconductor device, the methodcomprising: providing a workpiece, the workpiece comprising a materiallayer to be patterned disposed thereon; forming an anti-reflectivecoating over the material layer of the workpiece; forming a layer ofphotosensitive material over the anti-reflective coating; patterning thelayer of photosensitive material using a lithography mask, exposingportions of the anti-reflective coating; depositing a thin layer ofmaterial over the layer of photosensitive material and the exposedportions of the anti-reflective coating; etching the anti-reflectivecoating using the thin layer of material and the layer of photosensitivematerial as a mask, wherein the thin layer of material remains onsidewalls of the layer of photosensitive material; and patterning thematerial layer using at least the thin layer of material, the layer ofphotosensitive material, and the anti-reflective coating as a mask,wherein the thin layer of material enlarges a pattern transferred to thematerial layer from the lithography mask.
 20. The method according toclaim 19, wherein etching the anti-reflective coating using the thinlayer of material and the layer of photosensitive material as a maskcomprises using an etch process, wherein the etch process includes aredeposition component that forms on sidewalls of the anti-reflectivecoating during the etch process, wherein patterning the material layerfurther comprises using the redeposition component as the mask, andwherein the redeposition component further enlarges the patterntransferred to the material layer from the lithography mask.
 21. Themethod according to claim 19, wherein the thin layer of materialcomprises a polymer comprising a thickness of about 20 nm or less. 22.The method according to claim 19, wherein the material layer comprises aconductive material, a semiconductive material, an insulator, a hardmask, or combinations thereof.
 23. A method of manufacturing asemiconductor device, the method comprising: providing a workpiece;forming a material layer over the workpiece; forming a firstanti-reflective coating over the workpiece; disposing a firstphotosensitive material over the first anti-reflective coating; exposingthe first photosensitive material and the first anti-reflective coatingusing a first lithography mask, the first lithography mask comprising afirst portion of a pattern; developing the first photosensitivematerial, forming the first portion of the pattern in the firstphotosensistive material; using the first photosensitive material and/orthe first anti-reflective coating as a mask to form the first portion ofthe pattern in the material layer; removing the first photosensitivematerial and the first anti-reflective coating; forming a secondanti-reflective coating over the patterned material layer and exposedportions of the workpiece; disposing a second photosensitive materialover the second anti-reflective coating; exposing the secondphotosensitive material using a second lithography mask, the secondlithography mask comprising a second portion of a pattern, the secondportion of the pattern comprising a different pattern than the firstportion of the pattern and intersecting in regions with the firstportion of the pattern; developing the second photosensitive material,forming the second portion of the pattern in the second photosensistivematerial; forming a polymer material over the patterned secondphotosensitive material and over exposed portions of the secondanti-reflective coating; etching portions of the second anti-reflectivecoating using the polymer material and the patterned secondphotosensitive material as a mask using an anisotropic etch process; andusing the polymer material and the patterned second photosensitivematerial and/or the patterned second anti-reflective coating as a maskto pattern the material layer of the workpiece with an enlarged secondportion of the pattern.
 24. The method according to claim 23, whereinthe first lithography mask comprises a lithography mask for a pluralityof elongated transistor gates, wherein the second lithography maskcomprises a cutter lithography mask adapted to cut the ends of theplurality of elongated transistor gates patterned by the firstlithography mask, and wherein the polymer material decreases atip-to-tip distance between adjacent ends of transistor gates formed inthe material layer.
 25. The method according to claim 24, wherein alength of the transistor gates formed in the material layer is greaterthan a length of a pattern in the second lithography mask by about twicea thickness of the polymer material.
 26. The method according to claim23, wherein the anisotropic etch process for etching the secondanti-reflective coating using the polymer material and the secondphotosensitive material includes a redeposition component that forms onsidewalls of the second anti-reflective coating during the etch process,wherein patterning the material layer further comprises using theredeposition component as the mask, and wherein the redepositioncomponent further enlarges the second portion of the pattern transferredto the material layer from the second lithography mask.
 27. The methodaccording to claim 23, further comprising introducing a tapered profileto the material layer when using the polymer material and the patternedsecond photosensitive material and/or the patterned secondanti-reflective coating as a mask to pattern the material layer of theworkpiece.